T-HEAD-Staff Engineer, Chip Architect-Sunnyvale, US
In this role, you are supposed to be a member of SoC architecture team.
You will work with software and hardware engineering groups to define the next-generation high performance network interface controllers (NICs).
You will help build up a system-level C++ simulator for the target SoC, with new features implemented. You will use the simulator to study a range of performance, power, and cost trade-offs.
We expect you can
* Write C++ to implement new features and functional blocks in the simulator
* Analyze the workload of high-performance datacenter network to define the architecture of high-performance NIC
* Be responsible for drafting the architecture and microarchitecture specification
* Closely collaborate with the RTL design team for the microarchitecture design and performance correlation
* Work with software team to define the system architecture of next-generation high-performance network protocol stack and its applications
* Work in a cross-team and open-communication culture to collaborate with multiple teams in both the US and China to delegate tasks, set deadlines and ensure deliverables.
BS/MS/Ph.D. in Electronics Engineering with minimum of 5 years of chip design experiences
* Strong C++ coding skill (SystemC is a good plus)
* Strong background in Computer Architecture, including CPU, cache, DRAM, on-chip interconnect, NIC, PCIe and other I/Os
* Hands on experience in performance modeling and analysis (SystemC TLM is a good plus)
* Experience in workload analysis and characterization
* Experience in working with other to draft architecture and microarchitecture specification
* Design expertise in network area is a good plus, including switches, routers and network interface card.
* Hands on experience in high-performance NICs is a good plus, including RDMA (RoCEv2 or iWARP) and ToE
* Familiarity with TCP/IP protocol stack, as well as hands on experience on kernel or user-space networking stack is a good plus;
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