平头哥-Design Verification Engineer-上海
The Computing Technology Lab focuses on advanced research topics in computing, memory/storage, and interconnect technologies that can revolutionize today's computing systems with holistic innovations ranging from system architectures to VLSI designs, to enable new computing capabilities for improving energy efficiency and performance across multiple application domains, including both high-performance and embedded computing.
Therefore you will have excellent work opportunities with field leading experts from all different domains to change the world. And also we rapidly advance team members who have an outsized impact.
* Work with Architecture and Software teams to ensure micro-architecture and design is fully verified/validated across multiple platforms
* Contribute significantly to verification infrastructure development
* Development of System Verilog/UVM based protocol/traffic generators/checkers, development of test plan based on functional requirements
Masters degree desired, Bachelor's degree in CS/EE is required. 5+ years of relevant experience in ASIC verification field.
* Should have worked on developing/implementing test plans at the chip-level for complex ASICs.
* Fluent in System Verilog and scripting languages such as Python or Perl.
* Must have intimate knowledge of UVM methodology.
* Experience in the verification of SoC and other IPs such as CPU Subsystem, Ethernet, PCIE, DDR, Serdes etc.
* Knowledgeable about assertions and functional coverage
* Experience with code coverage, formal verification tools; familiarity with evolving verification methodologies.
* Very good communication skills and ability and desire to work in a geographically diverse team environment.
* Will be responsible for definition, development and execution of self-checking tests for complex digital ASICs
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