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平头哥-Staff Engineer, Physical Design

发布时间: 2019-09-02 工作地点: 森尼韦尔 工作年限: 五年以上
所属部门: 阿里集团 学   历: 本科 招聘人数: 若干

团队介绍:

The Computing Technology Lab focuses on advanced research topics in computing, memory/storage, and interconnect technologies that can revolutionize today's computing systems with holistic innovations ranging from system architectures to VLSI designs, to enable new computing capabilities for improving energy efficiency and performance across multiple application domains, including both high-performance and embedded computing.
Therefore you will have excellent work opportunities with field leading experts from all different domains to change the world. And also we rapidly advance team members who have an outsized impact.

岗位描述:

As a member of the PD team, you will build the next generation networking SoC in advanced process. You will drive the backend flow through the entire RTL2GDS process including floor planning, P&R, timing, PI, and sign-offs. You will also conduct PPA optimization.

You responsibilities include, but not limited to:
* Build backend flow on state-of-the-art processing node
* Create SPECs for PD sign-off
* Work closely with architecture and design team to optimize PPA
* Floor planning, design synthesis, equivalence checks, partitioning, IO assignment and IP integration, CTS and power grid, P&R , timing closure, power analysis etc.
* Design and timing ECOs and sign-offs

岗位要求:

BS or MS of EE, 5+ years of experience with the whole RTL2GDS process
* Understanding the state-of-the-art of processing node, custom lib and optimizations
* State-of-the-art experience with CTS and power grid planning, power integrity is a plus
* Experience with relatively large designs (>10m flops) on advanced process nodes and optimization methodology toward top performance and low power
* Understanding of DVFS, DFT, DFY, DFM is a plus

Some hands on with following tools are needed:
* Floor planning and P&R: Cadence Innovus and/or Synopsys ICC2
* Synthesis: Synopsys DC/DCG
* Formal Verification : Synopsys Formality and/or Cadence LEC
* STA: Primetime-DMSA
* PI : Apache Redhawk
* Physical Design Verification: Synopsys ICV, Mentor Calibre
* Scripting: TCL/Perl is required, Python is a plus

 

 

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