T-HEAD-Analog Design Chief Scientist-IoT
The analog design chief scientist will lead the analog and mixed signal team to design advance state-of-the-art Analog IPs, such as ultra low power IO, clock, power, codec and serdes. Define analog IP product roadmap and delivery schedule. Analog IP product definition, architecture, design, layout and test to guarantee a successful product.
1. Minimum MSEE with 15+ years or Ph.D. with 10+ years of relevant industry experience.
2. Hands-on experience in designing various analog and mixed signal integrated circuits such as high speed ADCs, DACs, wideband filters, amplifiers, LDO, reference circuits, oscillators, switched-capacitors circuits, I/O drivers. etc., in deep submicron technologies.
3. Ultra low power circuit design experience, such as near threshold and sub threshold technolgy.
4. Verilog-A/Verilog AMS behavioral modeling.
5. Deep understanding of analog circuit design techniques, sub-micron CMOS device physics and modeling, on-chip passives modeling, impedance matching, packaging effects, supply isolations and high speed analog/mixed-signal layout techniques.
6. Familiar with IC design CAD tools such as Spectre, SpectreRF, ADS, EMX, Virtuoso Layout, Calibre DRC/LVS/PEX, Matlab and Verilog-A/Verilog AMS.
7. Direct experience in IC bring up, debug and characterization using lab equipment.
8. Self-driven, excellent problem solving and analytical skills, good communication skills and a strong team player.
9. Local and international travel may be required.