The candidate will be the major interface to the IO analog/mixed signal design team or vendor. The candidate will be responsible for defining, implementing, and delivering fully functional and production ready chip IO Serdes infrastructure such as PCIE and DDR PHY, Die-to-Die interconnect. Detailed responsibilities include:
• All IOs and analog/mixed-signal hard IPs evaluation, selection and integration.
• Work with IP design team/IP vender on design review, quality control, schedule management.
• Participate in the IO related physical design, provide IO timing constraints for all related interfaces. Drive the mixed-signal IP integration
• Participate in the packaging design and focus on Serdes and Die-to-Die interconnect related issues.
• Tape-out review sign-offs, including Serdes PHY, DDRx PHY, PLL, Die-to-Die interconnect, Sensors.
• In Silicon bring up, coordinate the effort between system team, silicon team and IP vendors in bring up high speed IO interfaces, debug and resolve IP and hard IP issues
• Minimum MSEE with 10+ years or Ph.D. with 8+ years of relevant industry experience.
• Deep understanding of mixed signal high speed IO/PAD, DDRx PHY, and Serdes PHY design and architectures
• Must have hands-on experience of successful design and tape out high quality IO subsystem, PHY, PLL and another analog IP.
• Direct experience in PHY and Serdes bring up, debug and characterization using lab equipment.
• Self-driven, excellent problem solving and analytical skills, good communication skills and a strong team player.
• Local and international travel may be required.