你有机会和一流的芯片团队一起搭建高端芯片设计平台，参与新一代计算芯片的开发。作为芯片内PCIE IP的验证技术负责人, 确保IP的验证质量以满足业务需求.
* Work with Architecture and Software teams to ensure micro-architecture and design is fully verified/validated across multiple platforms
* Define testplan for specific block level design and execute the tesplan to achieve function verfication closure
* Development of reusable block level UVM verification enviroment with checker/monitor/driver etc,
* Masters degree desired, Bachelor's degree in CS/EE is required. 3+ years of relevant experience in ASIC verification field.
* Should have the test plan definition and execution experience
* Fluent in System Verilog and scripting languages such as Python or Perl.
* Must have intimate knowledge of UVM methodology.
* Experience in the verification of SoC and IO IPs such as PCIE, DDR, and peripherals such as UART/SPI/I2C/GPIO/TIMER/WATCHDOG etc.
* Knowledgeable about assertions and functional coverage
* Experience with code coverage, formal verification tools; familiarity with evolving verification methodologies.
* Experience with ARM based C/Assemblly test is a big plus
P.S. Please submit the English version of resume