Candidate will be responsible for
1. Plan design projects and help address the unique needs of our customers.
2. Review vendor capability to support development.
3. Participates in the development of Architecture and Microarchitecture specifications for the Logic components.
4. Provides IP integration support to SoC customers and represents RTL team.
5. Define micro-architecture of logic blocks while making power/performance/area (PPA) trade-offs and write detailed specifications.
6. Collaborate with design verification team to develop a detailed verification test-plan and support simulation bring-up/debug and bug fixes.
7. Use of various design tools (Linting, CDC, LEC, Fishtail, CLP etc.) to check and improve design quality Implementation of Low power logic, targeting power, performance, area, and timing goals.
5+ years ASIC/FPGA Digital design, verification, or related work experience.
1. Excellent problem solving skills and attention to detail
2. Great communication skills with ability to work independently or as part of a team
3. Experience with implementing high-speed data communication system.
4. ASIC design and verification experiences including architecture,
5. Experience with synthesis, and timing closure.
6. Experience with scripting tools (Perl/Python)
7. Experience with DC, LINT, LEC, and CDC.
8. Experience working in a multi-disciplinary, global team focused on advanced, high volume applications. Being familar with AXI/AHB/ACE bus protocols and SoC integration experiences.
9. Expreience with CCIX, CXL, QPI/UPI, and GenZ is plus.
10. Knowledge of cache coherence operations is big plus.
11. Ability to quickly react and adapt to changes.